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EISA
Enhanced ISA - расширенная архитектура промышленного стандарта.
Является расширением шины AT-Bus (ISA) и содержит в себе полностью копию
этой шины в (62+36)-контактном разъеме. Расширение шины заключено в
дополнительном ряде контактов в том-же разъеме. Стандартная частота - 8 МГц.
Предельная пропускная способность на стандартной частоте - 32Мб/с. Адресное
пространство организуется 32 битами и адресует 4ГБ ОЗУ. Имеет возможность
для захвата шины внешними устройствами, автоматическая настройка внешних
устройств, разделение каналов IRQ и DMA, арбитраж устройств на шине.
Все сигналы имеют TTL-уровни. Используется специальный двухярусный коннектор
с 62-pin и 36-pin гнездами. Upper block - Верхний ярус разъема - используется
для EISA расширения.
| Назначение |
Сигнал |
No
Pin |
| Ground | GND | B01 |
| Reset system3 | RESET DRV | B02 |
| Ucc +5V | +5V | B03 |
| Interrupt request 9 | IRQ9 | B04 |
| Ucc -5V | -5V | B05 |
| DMA request 2 | DRQ2 | B06 |
| Ucc -12V | -12V | B07 |
| No wait state4 | -NOWS | B08 |
| Ucc +12V | +12V | B09 |
| Ground | GND | B10 |
| Select Memory Write5 | -SMEMW | B11 |
| Select Memory Read6 | -SMEMR | B12 |
| I/O Write | IOW | B13 |
| I/O Read | IOR | B14 |
| DMA acknowledge 3 | -DACK3 | B15 |
| DMA request 3 | DRQ3 | B16 |
| DMA acknowledge 1 | -DACK1 | B17 |
| DMA request 1 | DRQ1 | B18 |
| Refresh memory | -REFRESH | B19 |
| System clock | SYSCLK | B20 |
| Interrupt request 7 | IRQ7 | B21 |
| Interrupt request 6 | IRQ6 | B22 |
| Interrupt request 5 | IRQ5 | B23 |
| Interrupt request 4 | IRQ4 | B24 |
| Interrupt request 3 | IRQ3 | B25 |
| DMA acknowledge 2 | -DACK2 | B26 |
| Terminal count7 | T/C | B27 |
| Buffered address latch enable | BALE | B28 |
| Ucc +5V | +5V | B29 |
| High Speed Clock8 | 14 MHz | B30 |
| Ground | GND | B31 |
| | | |
| Memory 16-bit10 | -MEM 16 | D01 |
| I/O 16-bit10 | -IO 16 | D02 |
| Interrupt request 10 | IRQ10 | D03 |
| Interrupt request 11 | IRQ11 | D04 |
| Interrupt request 12 | IRQ12 | D05 |
| Interrupt request 15 | IRQ15 | D06 |
| Interrupt request 14 | IRQ14 | D07 |
| DMA acknowledge 0 | -DACK0 | D08 |
| DMA request 0 | DRQ0 | D09 |
| DMA acknowledge 5 | -DACK5 | D10 |
| DMA request 5 | DRQ5 | D11 |
| DMA acknowledge 6 | -DACK6 | D12 |
| DMA request 6 | DRQ6 | D13 |
| DMA acknowledge 7 | -DACK7 | D14 |
| DMA request 7 | DRQ7 | D15 |
| Ucc +5V | +5V | D16 |
| DRQ gain control | -MASTER | D17 |
| Ground | GND | D18 |
|
No
Pin |
Сигнал |
Назначение |
| A01 | -I/O CH CK | I/O Channel Check |
| A02 | SD7 | Data bit 7 |
| A03 | SD6 | Data bit 6 |
| A04 | SD5 | Data bit 5 |
| A05 | SD4 | Data bit 4 |
| A06 | SD3 | Data bit 3 |
| A07 | SD2 | Data bit 2 |
| A08 | SD1 | Data bit 1 |
| A09 | SD0 | Data bit 0 |
| A10 | +I/O CH RDY | I/O Channel ready1 |
| A11 | AEN | Address enable2 |
| A12 | SA19 | Address bit 19 |
| A13 | SA18 | Address bit 18 |
| A14 | SA17 | Address bit 17 |
| A15 | SA16 | Address bit 16 |
| A16 | SA15 | Address bit 15 |
| A17 | SA14 | Address bit 14 |
| A18 | SA13 | Address bit 13 |
| A19 | SA12 | Address bit 12 |
| A20 | SA11 | Address bit 11 |
| A21 | SA10 | Address bit 10 |
| A22 | SA9 | Address bit 9 |
| A23 | SA8 | Address bit 8 |
| A24 | SA7 | Address bit 7 |
| A25 | SA6 | Address bit 6 |
| A26 | SA5 | Address bit 5 |
| A27 | SA4 | Address bit 4 |
| A28 | SA3 | Address bit 3 |
| A29 | SA2 | Address bit 2 |
| A20 | SA1 | Address bit 1 |
| A31 | SA0 | Address bit 0 |
| | | |
| C01 | SBHE | System bus high enable9 |
| C02 | LA23 | Latchable Address bit 23 |
| C03 | LA22 | Latchable Address bit 22 |
| C04 | LA21 | Latchable Address bit 21 |
| C05 | LA20 | Latchable Address bit 20 |
| C06 | LA19 | Latchable Address bit 19 |
| C07 | LA18 | Latchable Address bit 18 |
| C08 | LA17 | Latchable Address bit 17 |
| C09 | -MEMR | Memory read5 |
| C10 | -MEMW | Memory write6 |
| C11 | SD8 | Data bit 8 |
| C12 | SD9 | Data bit 9 |
| C13 | SD10 | Data bit 10 |
| C14 | SD11 | Data bit 11 |
| C15 | SD12 | Data bit 12 |
| C16 | SD13 | Data bit 13 |
| C17 | SD14 | Data bit 14 |
| C18 | SD15 | Data bit 15 |
|
| Upper block |
| Ground | GND | B01 |
| Ucc +5V | +5Vdc | B02 |
| Ucc +5V | +5Vdc | B03 |
| Reserved | - | B04 |
| Reserved | - | B05 |
| | KEY | B06 |
| Reserved | - | B07 |
| Reserved | - | B08 |
| Ucc +12V | +12Vdc | B09 |
| Memory-I/O11 | M-IO | B10 |
| Lock memory12 | -LOCK | B11 |
| Reserved | - | B12 |
| Ground | GND | B13 |
| Reserved | - | B14 |
| Byte enable 3 | -BE3 | B15 |
| | KEY | B16 |
| Byte enable 2 | -BE2 | B17 |
| Byte enable 0 | -BE0 | B18 |
| Ground | GND | B19 |
| Ucc +5V | +5Vdc | B20 |
| Latchable address 29 | LA29 | B21 |
| Ground | GND | B22 |
| Latchable address 26 | LA26 | B23 |
| Latchable address 24 | LA24 | B24 |
| | KEY | B25 |
| Latchable address 16 | LA16 | B26 |
| Latchable address 14 | LA14 | B27 |
| Vcc +5V | +5Vdc | B28 |
| Vcc +5V | +5Vdc | B29 |
| Ground | GND | B30 |
| Latchable address 29 | LA10 | B31 |
| | | |
| Latchable address 8 | LA8 | D01 |
| Latchable address 6 | LA6 | D02 |
| Latchable address 5 | LA5 | D03 |
| Vcc +5V | +5Vdc | D04 |
| Latchable address 2 | LA2 | D05 |
| | KEY | D06 |
| Data bit 16 | SD16 | D07 |
| Data bit 18 | SD18 | D08 |
| Ground | GND | D09 |
| Data bit 21 | SD21 | D10 |
| Data bit 23 | SD23 | D11 |
| Data bit 24 | SD24 | D12 |
| Ground | GND | D13 |
| Data bit 27 | SD27 | D14 |
| | KEY | D15 |
| Data bit 29 | SD29 | D16 |
| Vcc +5V | +5Vdc | D17 |
| Vcc +5V | +5Vdc | D18 |
| Grant bus access | -MACK | D19 |
|
| Upper block |
| A01 | -CMD | Timing control CMD |
| A02 | -START | Start of cycle |
| A03 | EXRDY | Request wait state |
| A04 | -EX32 | Slave Support 32-bit |
| A05 | GND | Ground |
| A06 | KEY | |
| A07 | -EX16 | Slave Support 16-bit |
| A08 | -SLBURST | Slave Support burst |
| A09 | -MSBURST | Slave Bus Master sup. |
| A10 | W-R | Read-Write cycle |
| A11 | GND | Ground |
| A12 | - | Reserved |
| A13 | - | Reserved |
| A14 | - | Reserved |
| A15 | GND | Ground |
| A16 | KEY | |
| A17 | -BE1 | Byte enable 1 |
| A18 | LA31 | Latchable address bit 31 |
| A19 | GND | Ground |
| A20 | LA30 | Latchable address bit 30 |
| A21 | LA28 | Latchable address bit 28 |
| A22 | LA27 | Latchable address bit 27 |
| A23 | LA25 | Latchable address bit 25 |
| A24 | GND | Ground |
| A25 | KEY | |
| A26 | LA15 | Latchable address bit 15 |
| A27 | LA13 | Latchable address bit 13 |
| A28 | LA12 | Latchable address bit 12 |
| A29 | LA11 | Latchable address bit 11 |
| A20 | GND | Ground |
| A31 | LA9 | Latchable address bit 9 |
| | | |
| C01 | LA7 | Latchable Address bit 7 |
| C02 | GND | Ground |
| C03 | LA4 | Latchable Address bit 4 |
| C04 | LA3 | Latchable Address bit 3 |
| C05 | GND | Ground |
| C06 | KEY | |
| C07 | SD17 | Data bit 17 |
| C08 | SD19 | Data bit 19 |
| C09 | SD20 | Data bit 20 |
| C10 | SD22 | Data bit 22 |
| C11 | GND | Ground |
| C12 | SD25 | Data bit 25 |
| C13 | SD26 | Data bit 26 |
| C14 | SD28 | Data bit 28 |
| C15 | KEY | |
| C16 | GND | Ground |
| C17 | SD30 | Data bit 30 |
| C18 | SD31 | Data bit 31 |
| C19 | -MREQx | Request Bus access13 |
|
| 
